FIG. 3 shows a prior art soldering type flip-chip, and FIGS. 4 and 5 show processes for producing the prior art soldering flip-chip. In these Figures the reference numeral 6 designates a wafer, and the reference numeral 1 designates an electrode portion comprising e.g. aluminum produced on said wafer 6. The reference numeral 2 designates a passivation film deposited on the wafer 6 except for the electrode portion 1. The reference numeral 7 designates a solder film, the reference numeral 7a designates a solder lump, the reference numeral 8 designates a soldering bump of a spherical shape formed on the electrode portion 1. The reference numeral 3 designates a barrier metal layer deposited between the electrode portion 1 and the soldering bump 8. In this case, chrome, copper, and gold are subsequently vapor plated to constitute a triple layer structure of this barrier metal layer.
The method of producing this prior art semiconductor device will be described.
At first, an aluminum film is deposited on a wafer 6 by a vapor plating method or a spattering method, and this aluminum film is patterned to obtain wirings, and the aluminum electrode portion 1 is formed so as to obtain an electrical contact with a substrate. Next, a passivation film 2 is deposited on the entire surface of the wafer 6 by a CVD method or a spattering method, and the passivation film 2 on the aluminum electrode portion 1 is removed by photolithographic etching. In this way, a usual chip structure is constructed, and then a bump is produced. Chrome, copper, and gold are subsequently vapor plated on the entire surface of the chip to produce a triple layer, and this triple layer is etched except for the portion on the aluminum electrode portion 1 to form the barrier metal layer 3 which enhances the wetness of the solder on the aluminum electrode portion 1 and strengthens the adhesion. Thereafter, solder is vapor plated to cover the barrier metal layer 3, and the solder film 7 is deposited having a circular configuration several hundreds of microns in diameter and several tens .mu.m thickness to obtain a structure shown in FIG. 4. Thereafter, this is heated to melt the solder film 7, and a spherical shaped solder bump 8 of about 100 .mu.m diameter is formed as shown in FIG. 3 by the surface tension of solder.
Also, it is also possible to obtain the structure shown in FIG. 3 by heating the one shown in FIG. 5. In order to obtain this structure shown FIG. 5, a barrier metal layer 3 is produced by a similar method as the above described one, and a resist film is vapor plated on the entire surface of the wafer 6 to a thickness of 5 to 10 .mu.m, and the resist on the aluminum electrode portion 1 is removed by photolithography, and the solder lump 7a of about 40 to 80 .mu.m thickness is deposited on the barrier metal layer 3 by solder plating, and thereafter the resist is removed.
By using this bump shown in FIG. 3 formed in this way it is possible to conduct a bonding for the connection terminal on the chip directly to the connection terminal on the substrate, that is, a facedown bonding. With this facedown bonding, it is possible to conduct a higher reliable bonding than the wire bonding at approximately the same expense over some range of the number of connection terminals. This enables the conducting of high density mounting at a low cost.
In the prior art soldering type flip-chip with such a construction, it is quite difficult to control the height of the individual soldering vamp with high precision, and when the number of connection terminals for connection to the substrate is increased, it is difficult to conduct a bonding for each terminal to the substrate evenly. Furthermore, when the distance between the substrate and the chip is short, there may arise a leak due to the overflow of the solder, and therefore it is required to maintain a predetermined distance between the substrate and the chip. Furthermore, in producing a soldering bump on a chip surface it is required that a vapor plating of solder in a region of several hundreds of microns in diameter be conducted as in the structure shown in FIG. 4. This provides for shortening of the distance between adjacent terminals to a value smaller than the above-described one, resulting in an disadvantageous factor against an increase in the number of terminals.